1. Technical Field
The present invention relates to semiconductor devices in general and, in particular, to memory devices. Still more particularly, the present invention relates to an apparatus for increasing pulldown rate of a bitline within a memory device during a read operation.
2. Description of the Prior Art
Static random access memories (SRAMs) are commonly utilized within high-speed computer systems. A typical SRAM circuit includes multiple storage cells arranged in an array. Each column of the array has two complementary bitlines for reading a stored digital value from and for writing a new digital value to one of the storage cells within the column. Complementary bitlines enables a read circuit, such as a sense amplifier, to utilize differential sensing techniques for evaluating the state of a storage cell. When implementing a differential sensing scheme using complementary bitlines, a circuit designer must take into account the voltage range to which the complementary bitlines should be charged. The smaller the voltage range, the more efficient the differential sensing scheme becomes. However, a sense amplifier having a relatively small voltage range is also more prone to noise interferences.
In order to improve read and write access speed, a precharge circuit is typically utilized to initialize bitlines to a high state before a read operation. The result is storage cells having rapid access times for both read and write operations and having considerable stability when switching from one state to another. During a read operation, one of the many storage cells within a column may pull a bitline from its precharged logic high state down to a logic low state. However, because of the capacitive load attributed by other storage cells within the same column, the pulldown rate of the bitline may tend to be relatively slow. Thus, it would be desirable to provide an apparatus for increasing the pulldown rate of a bitline during a read operation.
In accordance with a preferred embodiment of the present invention, a memory device includes a pair of complementary differential bitlines, and each of the complementary differential bitlines has a precharge transistor. The memory device also includes multiple storage cells coupled between the complementary differential bitlines. Furthermore, each of the complementary differential bitlines has a discharge transistor for increasing the pulldown rate of a respective bitline during a read operation.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.